Memory arrays are electronic devices that store digital data. An exemplary type of memory array is a random access memory (“RAM”) array typically found in personal computers, smartphones, and the like. There are multiple types of RAM arrays including static RAM (“SRAM”) arrays and dynamic RAM (“DRAM”) arrays. The data stored by an SRAM array is retrained so long as power is supplied to the memory array, whereas the data stored by a DRAM array typically must be periodically refreshed.
The memory industry is continually seeking to improve the attributes of power consumption, read access time, and memory capacity of all types of memory arrays. The relationship within each attribute and between attributes is complex and each attribute has multiple contributing factors. Power consumption includes the electrical power consumed by the memory array during read cycles, write cycles, restore cycles, as well as the electrical power consumed by the memory array to refresh the stored values. These power consumption attributes in turn are affected by noise sensitivity, retention time, leakage currents, and the threshold voltage of transistors within the memory arrays. Read access time is affected by the rate and amplitude of bit line voltage changes, delay, and required clock cycles. Capacity of the memory array is affected by technology node, architecture (e.g. one transistor (1T), two transistor (2T), three transistor (3T), or six transistor (6T)) and the number of bits stored per cell. In addition, when one memory array attribute is improved, a tradeoff is typically needed with one or more of the other attributes. For example, when power consumption is decreased read access time increases and/or capacity decreases.
Recent approaches in improving memory arrays have (i) reduced the read access time at the expense of capacity, and (ii) increased memory capacity at the expense of power consumption. Both of these approaches also suffer from issues including full-scale signal swings on high capacitance bit lines, a read implementation based on charge sharing, and a destructive read process. The first two issues ultimately cause higher power consumption and the latter issue lengthens read access time.
Therefore, it is desirable to provide a logic-compatible memory architecture that effectively reduces read power requirements of the memory array and increases the capacity of the memory array, while maintaining suitable read access times.